1. Field of the Invention
This invention is in the field of integrated circuit memories. More particularly, it relates to a Static Random Access Memory ("SRAM") which does not require a separate write signal to the bit line load structures of the SRAM during the write cycle to decouple the load structures from the SRAM memory cells.
2. Description of the Relevant Art
Integrated circuit memories which do not require periodic refreshing to maintain integrity of the data stored within them, in particular, SRAMs, are known. Typically, an SRAM memory is constructed by fabricating an array of memory cells and peripheral circuitry on a single integrated circuit chip. Using present manufacturing techniques, state of the art SRAMs incorporate about one million cells.
An example of an SRAM memory cell is shown in FIG. 1. Memory cell 10 comprises flip-flop transistors 13 and 14, gating transistors 15 and 16 and load resistors 11 and 12. The cell is individually accessed by means of the word line, and output signals from the cell are provided on the Bit and Bit lines. Although the construction and operation of such a memory cell is known, a brief review is appropriate to establish the operational environment of the present invention.
Transistor 14 and resistor 12 are the driver and load of an inverter that is cross-coupled to a second inverter formed from transistor 13 and resistor 11. Together, the two inverters form a storage flip-flop. Transistors 15 and 16, when on, couple the output of the flip-flop to the Bit and Bit lines, which provide the memory cell's information to an output sense amplifier (not shown).
The technique for reading the cell is as follows. In a quiescent state, the word line is at V.sub.ss potential, which isolates the memory cell from the Bit and Bit lines as transistors 15 and 16 do not conduct when their gates are at V.sub.ss potential. If the binary information stored in the cell is such that transistor 14 is assumed to be on, then node A will be at V.sub.dd. To read the memory cell, the word line is pulsed high. This turns on both transistors 15 and 16. As node A is at approximately V.sub.dd, current will flow through the Bit line. A load structure on the bit lines, not shown in FIG. 1, establishes a differential voltage on the bit lines by means of the cell current through the load. When the Read command turns on transistors 15 and 16, the current flowing through the Bit line will be compared to the current flowing through the BIT line by a differential sense amplifier (not shown). Depending upon the relative potentials of Bit and Bit, the information from the memory cell will be considered a binary 0 or 1.
Writing to the cell requires that the appropriate values be placed on the Bit or BIT line by write amplifiers (not shown). The word line is then pulsed and nodes A and B are reset to the desired voltage as necessary. Both bit lines must be driven simultaneously when a write is commanded.
FIG. 2 illustrates how individual memory cells are interconnected into an SRAM. The individual memory cells are arranged in row and columns. The numbers in the lower right corner of each cell indicate the row and column in which the cell is situated. Each row has an address line, here labeled Word.sub.0, Word.sub.1 and Word.sub.n, coupled to each cell. Additionally, each column of memory cells is coupled to separate Bit and Bit lines. In addition to the load structure for each individual memory cell, each column of memory cells has a load structure to provide the necessary voltage differential for the sense amplifier.
Referring back to FIG. 1, resistors 11 and 12 comprise a passive load structure for a single memory cell. In addition to this type of load structure for memory cell 10 shown in FIG. 1, other load structures can be used. FIG. 3A shows how resistors 11 and 12 of FIG. 1 could be replaced by NMOS transistors 17 and 18; the drains and gates of both transistors being coupled to the memory cell's voltage supply. FIG. 3B shows how PMOS transistors could be used to construct the load structure.
FIG. 4 is a graph illustrating the change in voltages on the Bit and Bit lines when a transition is made from one cell to another cell on the same column during a read cycle, for example when a read operation first reads one cell in a column, then reads another cell in the same column. In the example of FIG. 4, the information contained in the first cell is the inverse of the information in the other cell. During the transition between the two read operations, the voltage on the Bit line starts dropping as the voltage on the Bit line begins to rise. The minimum time required for the Bit line voltage to equal and then exceed the Bit line voltage, labeled in FIG. 4 as .DELTA.T, is referred to as the memory cell's switching time. The switching time determines the overall speed of the memory. Any technique which can speed either the fall or rise time of either or both the Bit or Bit line will improve overall memory performance.
The switching time is determined by numerous factors. For purposes of this invention, one of the most important factors is the Resistor/Capacitor ("RC") time constant, which is created by the capacitances present on the Bit and Bit lines and the resistance of the bit line column load structure. The capacitance on the Bit and Bit lines results from the intrinsic capacitance of the drains of transistors 15 and 16 in FIG. 1. The resistance is mainly a function of the bit line column load's resistance. As is apparent, lowering the resistance will have a direct beneficial effect on the switching time, by reducing the RC time constant. One method of reducing the R value is to use larger NMOS or PMOS transistors, resulting in an improvement in the switching time. With larger transistors, the differential between the logic 0 and 1 voltage levels is smaller and the resistance is less.
Certain active techniques have also been used to improve the switching time. One bit line column load structure embodying a technique called Address Transition Detection is shown in FIG. 5. In circuit 20, transistors 27 and 29 are PMOS transistors and serve as the bit line load for a column of memory cells. Transistors 21, 23 and 25 form a pull-up network. When an address input transition occurs, the EQ ("Equalize") node is pulsed low. This turns on transistors 21 through 25 thereby placing additional resistance in parallel with load transistors 27 and 29. This decreases the resistance of the load, resulting in a harder and faster pull-up to the high voltage, and shorts both bit lines to the same high voltage level. Now, when the new memory cell is accessed, the bit lines have already been shorted together, thereby establishing a high voltage level on both nodes. The new cell only needs have to pull the voltage low on one of the nodes to complete the switching of the voltage levels, establishing new voltage differentials for reading.
Unfortunately, the bit line column load structure suffers from certain disadvantages when it is necessary to write a value to the memory cell. When a new value is written to a given memory cell, the old value must be destroyed. One way of doing this is to discharge the voltage at either node A or B (FIG. 1) to V.sub.ss, the ground potential. This is done by pulling Bit or Bit low to write the low level into the cell. Unfortunately, the bit line load structure in the SRAM memory holds the bit line nodes to almost V.sub.dd. Therefore, to change the voltages on nodes A and B, it is necessary to decouple the memory cell from its bit line load structure.
One bit line column load structure which can be decoupled during write operations is shown in FIG. 6. In the illustrated circuit, when the Write Enable ("WE") signal goes high, PMOS transistors 32 and 33 turn off, reducing the load on the bit lines. Although this type of circuit functions adequately, the necessity of having a separate WE signal provided to the memory cell bit line loads is undesirable as the signal must be decoded before it can be transmitted to the proper column of memory cells in a large array, thereby slowing circuit operation.
A need exists for a load structure for a column of memory cells which can be decoupled from the column of memory cells without the use of a separate "release" signal and which can decrease the switching time for the memory cell to which it is coupled.